The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a multilayer interconnection structure and a fabrication process thereof.
With the progress in the art of photolithography, integration density of integrated circuits is increasing continuously every year, and the number of active devices formed on a common semiconductor chip is increasing ever and ever.
In order to interconnect such active devices formed on a single semiconductor chip, recent integrated circuits tend to use a multilayer interconnection structure in which conductor patterns are covered by an interlayer insulation film and the conductor pattern of the next layer is formed on the foregoing interlayer insulation film. By repeating such a structure, it is possible to provide a complex wiring pattern for the active devices formed on the semiconductor chip.
On the other hand, such a continuous increase of integration density has raised the problem of transmission delay of signals caused inside the integrated circuit as a result of the resistance and capacitance of the complex interconnection patterns formed in the multilayer interconnection structure. Thus, in order to minimize the problem of signal transmission delay as much as possible, recent integrated circuits tend to use a low-resistance Cu pattern in a multilayer interconnection structure, in combination with an organic interlayer insulation film characterized by a low-dielectric constant.
In view of the difficulty of patterning a Cu layer by a conventional dry etching process, such a multilayer interconnection structure that uses a Cu interconnection pattern is generally formed according to the dual damascene process in which interconnection grooves and contact holes are formed first in an interlayer insulation film in correspondence to the desired interconnection pattern, followed by the deposition process of a Cu layer such that the Cu layer thus deposited fills the interconnection grooves and the contact holes. After the deposition of the Cu layer, a chemical mechanical polishing (CMP) process is applied and the part of the Cu layer located above the interlayer insulation film is polished away. Thereby, a planarized structure suitable for forming a second interconnection layer thereon is obtained easily.
It should be noted that the foregoing dual damascene process, not relying on the dry etching process for forming a conductor pattern, is advantageous in forming the interconnection patterns with a large aspect ratio. Further, the dual damascene process successfully overcomes the difficulty of covering the conductor patterns repeated with a minute pitch by means of an interlayer insulation film. Thus, dual damascene process is thought to be an advantageous process of forming a multilayer interconnection structure including therein extremely minute conductor patterns. The foregoing effect of the dual damascene process for reducing the cost of the semiconductor device is particularly significant for the semiconductor devices in which the interconnection pattern of the multilayer interconnection structure has an increased aspect ratio and formed with a decreased pitch.
FIGS. 1A-1F show a typical example of the conventional dual damascene process of forming a multilayer interconnection structure that uses an SiO.sub.2 interlayer insulation film.
Referring to FIG. 1A, a substrate 1 of Si carries thereon a lower interconnection pattern 10 of a conductive material such as Cu, with an insulation film (not illustrated) interposed between the Si substrate 1 and the lower interconnection pattern 10. Further, a first etching stopper film 12 of SiN is formed on the lower interconnection pattern 10 by way of a plasma CVD process, and a first interlayer insulation film 14 of SiO.sub.2 is formed further on the etching stopper film 12 by a plasma CVD process. The first interlayer insulation film 14 is then covered by a second etching stopper film 16 of SiN formed by a plasma CVD process, and the second etching stopper film 16 is covered by a resist pattern 18, wherein the resist pattern 18 includes a resist window 18A formed in correspondence to the contact hole to be formed in the multilayer interconnection structure.
Next, in the step of FIG. 1B, a dry etching process is applied to the SiN film 16 while using the resist pattern 18 as a mask, and there is formed an opening 20 in the SiN film 16 in correspondence to the resist window 18A. After the formation of the opening 20, the resist pattern 18 is removed by an asking process.
Next, in the step of FIG. 1C, an SiO.sub.2 film 22 is formed on the SiN film 16 by a CVD process as a second interlayer insulation film such that the second interlayer insulation film 22 covers the foregoing opening 20, and a step of FIG. 1D is conducted subsequently in which a resist pattern 24 having a resist window 24A corresponding to the interconnection groove to be formed in the SiO.sub.2 film 22, is provided on the SiO.sub.2 film 22.
Next, in the step of FIG. 1E, the SiO.sub.2 film 22 is subjected to a dry etching process while using the resist film 24 as a mask, to form an interconnection groove 26 in the SiO.sub.2 film in correspondence to the resist window 24A of the resist pattern 24. It should be noted that the interconnection groove 26 exposes the SiN film 16 at the bottom surface thereof.
By continuing the dry etching process of FIG. 1E further after the exposure of the SiN film 16 in the interconnection groove 26, the dry etching proceeds into the SiO.sub.2 film 14 and there is formed a contact hole 28 in the SiO.sub.2 film 14. The contact hole 28 exposes the SiN film 12 at the bottom part thereof.
Next, in the step of FIG. 1F, the SiN film 12 exposed at the bottom part of the contact hole 28 is removed by an etching process, and the interconnection groove 26 and the contact hole 28 are filled with Cu by depositing a Cu layer (not shown) on the SiO.sub.2 film 22 and causing a reflowing in the Cu layer thus deposited.
By employing the dual damascene process as noted above, the interconnection groove and the contact hole are formed by a single dry etching process, and the fabrication process of the semiconductor device is facilitated substantially.
On the other hand, the foregoing multilayer interconnection structure has a drawback, due to the use of SiO.sub.2 having a large dielectric constant, for the interlayer insulation film 14 or 22, in that the interconnection patterns tend to have a large stray capacitance. Thereby, the multilayer interconnection structure cannot eliminate the foregoing problem of signal transmission delay caused by the stray capacitance.
In order to overcome the foregoing problem, it is proposed to provide a multilayer interconnection structure that uses an organic interlayer insulation film having a characteristically small dielectric constant.
FIGS. 2A-2E show the process of forming such a conventional multilayer interconnection structure that uses an organic interlayer insulation film, wherein those parts corresponding to the parts described previously are designated with the same reference numerals and the description thereof will be omitted.
Referring to FIG. 2A, the Cu interconnection pattern 10 on the Si substrate 1 is covered by an etching stopper film 30 of SiN formed by a plasma CVD process similarly to the multilayer interconnection structure explained above, except that the etching stopper film 30 carries thereon an organic SOG film 32 formed by a spin coating process as the first interlayer insulation film. Further, a second etching stopper film 34 of SiN is formed on the organic SOG film 32 by a plasma CVD process and another organic SOG film 36 is formed on the etching stopper film 34 by a spin coating process as the second interlayer insulation film.
The organic SOG film 36 is then covered with a resist pattern 38 having a resist window 38A corresponding to the contact hole to be formed in the organic SOG film 32, and a step of FIG. 2B is conducted in which the organic SOG film 36, the SiN film 34 and the organic SOG film 32 are consecutively etched with a dry etching process while using the resist pattern 38 as a mask, to form a contact hole 40 exposing the SiN etching stopper film 30.
Next, in the step of FIG. 2C, the resist pattern 38 is removed and a resist pattern 42 is formed on the organic SOG film 36 such that the resist pattern 42 includes a resist window 42A exposing the foregoing contact hole 40 formed in the step of FIG. 2B. Further, by applying a dry etching process to the organic SOG film 36 in the step of FIG. 2D while using the resist pattern 42 as a mask, there is formed an interconnection groove 44 in the organic SOG film 36 in correspondence to the resist window 42A such that the SiN film 34 is exposed at the bottom of the interconnection groove 44.
After removing the resist pattern 42 by an asking process, the SiN film 34 is removed from the bottom of the interconnection groove 44 by an etching process. Simultaneously, the SiN film 30 at the bottom of the contact hole 40 is removed, and Cu interconnection pattern 10 on the substrate 1 is exposed at the contact hole 40.
In the latter process explained with reference to FIGS. 2A-2E, the process of forming the contact hole 40 and the process of forming the interconnection groove 44 are conducted separately by using respective mask processes.
The organic interlayer insulation films 32 and 36 explained with reference to FIGS. 2A-2E are applicable also to the process of FIGS. 1A-1F. Further, the inorganic interlayer insulation films 14 and 22 explained with reference to FIGS. 1A-1F can be used also in the process of FIGS. 2A-2E.
On the other hand, the conventional multilayer interconnection structure using therein the organic interlayer insulation film suffers from the problem, when there arises a misalignment in the resist pattern 24 as represented in FIG. 3A, in that the opening 20 is not included, or only partly included, in the interconnection groove 26 formed in the SiO.sub.2 film 22.
When a dry etching process is conducted in the state of FIG. 3A to form the contact hole 28 without correcting the resist pattern 24, the contact hole 28 thus formed may have a size substantially smaller than the designed size as represented in FIG. 3B. Alternatively, no contact hole may be formed at all. A similar problem arises also in the multilayer interconnection structure of FIGS. 2A-2E.
When such a misalignment is caused in the resist pattern 24, the resist pattern 24 can be corrected by simply issolving the defective resist pattern 24 in to a solvent and proving g a new resist pattern 24. This correction of the resist pattern is achieved easily and without problem when the interlayer insulation film 22 is formed of an inorganic material such as SiO.sub.2.
When the interlayer insulation film 22 is formed of a low-dielectric, organic SOG as in the case of FIGS. 2A-2E, on the other hand, such a correction of the resist pattern raises a problem explained hereinafter with reference to FIGS. 4A-4D.
Referring to FIG. 4A, the resist pattern 38 is formed on an SiO.sub.2 film 60 covering the organic SOG film 36, and an opening 60A is formed in the step of FIG. 4B in the SiO.sub.2 film 60 while using the resist pattern 38 as a mask, such that the opening 60A corresponds to the resist window 38A.
Next, in the step of FIG. 4C, the resist pattern 38 is removed and a contact hole 62 is formed in the SOG films 36 and 32, such that the contact hole 62 extends through the organic SOG films 36 and 32 and further through the intervening SiN film 34.
After the step of FIG. 4C, the step of FIG. 4D is conducted in which a resist pattern 64 having a resist window 64A is formed on the SiO.sub.2 film 60 such that the resist window 64A exposes the contact hole 62, wherein the resist window 64A formed in the step of FIG. 4D may have a positional error such that the resist pattern 64 cover the contact hole 62 completely or partially, similarly to the case of FIGS. 3A and 3B.
When the resist window 64A of the resist pattern 64 has a positional offset as represented in FIG. 4D, it is necessary to remove the resist pattern 64 by an asking process for re-deposition and patterning of the resist pattern 64. However, because of the fact that the organic SOG film 36 is exposed at the side wall of the contact hole 62 in the structure of FIG. 4C or 4D, such a removal of the resist pattern 64 would inevitably cause an erosion in the organic SOG film 36 in correspondence to the contact hole 62. In other words, it has not been possible to re-form the resist pattern 64 when there is an error in the position of the resist window 64A. Thereby, it has been difficult to increase the yield of production of the semiconductor device.